/***************************************************************************//**
* \file cyreg_prot.h
*
* \brief
* PROT register definition header
*
* \note
* Generator version: 1.6.0.217
* Database revision: TVIIBE4M_WW2014_BTO
*
********************************************************************************
* \copyright
* Copyright 2016-2020, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/

#ifndef _CYREG_PROT_H_
#define _CYREG_PROT_H_

#include "cyip_prot_v2.h"

/**
  * \brief SMPU structure (PROT_SMPU_SMPU_STRUCT0)
  */
#define CYREG_PROT_SMPU_SMPU_STRUCT0_ADDR0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR0_t*) 0x40232000UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT0_ATT0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT0_t*) 0x40232004UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT0_ADDR1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR1_t*) 0x40232020UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT0_ATT1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT1_t*) 0x40232024UL)

/**
  * \brief SMPU structure (PROT_SMPU_SMPU_STRUCT1)
  */
#define CYREG_PROT_SMPU_SMPU_STRUCT1_ADDR0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR0_t*) 0x40232040UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT1_ATT0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT0_t*) 0x40232044UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT1_ADDR1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR1_t*) 0x40232060UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT1_ATT1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT1_t*) 0x40232064UL)

/**
  * \brief SMPU structure (PROT_SMPU_SMPU_STRUCT2)
  */
#define CYREG_PROT_SMPU_SMPU_STRUCT2_ADDR0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR0_t*) 0x40232080UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT2_ATT0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT0_t*) 0x40232084UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT2_ADDR1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR1_t*) 0x402320A0UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT2_ATT1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT1_t*) 0x402320A4UL)

/**
  * \brief SMPU structure (PROT_SMPU_SMPU_STRUCT3)
  */
#define CYREG_PROT_SMPU_SMPU_STRUCT3_ADDR0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR0_t*) 0x402320C0UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT3_ATT0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT0_t*) 0x402320C4UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT3_ADDR1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR1_t*) 0x402320E0UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT3_ATT1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT1_t*) 0x402320E4UL)

/**
  * \brief SMPU structure (PROT_SMPU_SMPU_STRUCT4)
  */
#define CYREG_PROT_SMPU_SMPU_STRUCT4_ADDR0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR0_t*) 0x40232100UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT4_ATT0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT0_t*) 0x40232104UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT4_ADDR1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR1_t*) 0x40232120UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT4_ATT1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT1_t*) 0x40232124UL)

/**
  * \brief SMPU structure (PROT_SMPU_SMPU_STRUCT5)
  */
#define CYREG_PROT_SMPU_SMPU_STRUCT5_ADDR0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR0_t*) 0x40232140UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT5_ATT0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT0_t*) 0x40232144UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT5_ADDR1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR1_t*) 0x40232160UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT5_ATT1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT1_t*) 0x40232164UL)

/**
  * \brief SMPU structure (PROT_SMPU_SMPU_STRUCT6)
  */
#define CYREG_PROT_SMPU_SMPU_STRUCT6_ADDR0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR0_t*) 0x40232180UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT6_ATT0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT0_t*) 0x40232184UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT6_ADDR1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR1_t*) 0x402321A0UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT6_ATT1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT1_t*) 0x402321A4UL)

/**
  * \brief SMPU structure (PROT_SMPU_SMPU_STRUCT7)
  */
#define CYREG_PROT_SMPU_SMPU_STRUCT7_ADDR0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR0_t*) 0x402321C0UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT7_ATT0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT0_t*) 0x402321C4UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT7_ADDR1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR1_t*) 0x402321E0UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT7_ATT1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT1_t*) 0x402321E4UL)

/**
  * \brief SMPU structure (PROT_SMPU_SMPU_STRUCT8)
  */
#define CYREG_PROT_SMPU_SMPU_STRUCT8_ADDR0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR0_t*) 0x40232200UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT8_ATT0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT0_t*) 0x40232204UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT8_ADDR1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR1_t*) 0x40232220UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT8_ATT1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT1_t*) 0x40232224UL)

/**
  * \brief SMPU structure (PROT_SMPU_SMPU_STRUCT9)
  */
#define CYREG_PROT_SMPU_SMPU_STRUCT9_ADDR0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR0_t*) 0x40232240UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT9_ATT0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT0_t*) 0x40232244UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT9_ADDR1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR1_t*) 0x40232260UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT9_ATT1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT1_t*) 0x40232264UL)

/**
  * \brief SMPU structure (PROT_SMPU_SMPU_STRUCT10)
  */
#define CYREG_PROT_SMPU_SMPU_STRUCT10_ADDR0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR0_t*) 0x40232280UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT10_ATT0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT0_t*) 0x40232284UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT10_ADDR1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR1_t*) 0x402322A0UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT10_ATT1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT1_t*) 0x402322A4UL)

/**
  * \brief SMPU structure (PROT_SMPU_SMPU_STRUCT11)
  */
#define CYREG_PROT_SMPU_SMPU_STRUCT11_ADDR0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR0_t*) 0x402322C0UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT11_ATT0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT0_t*) 0x402322C4UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT11_ADDR1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR1_t*) 0x402322E0UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT11_ATT1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT1_t*) 0x402322E4UL)

/**
  * \brief SMPU structure (PROT_SMPU_SMPU_STRUCT12)
  */
#define CYREG_PROT_SMPU_SMPU_STRUCT12_ADDR0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR0_t*) 0x40232300UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT12_ATT0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT0_t*) 0x40232304UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT12_ADDR1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR1_t*) 0x40232320UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT12_ATT1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT1_t*) 0x40232324UL)

/**
  * \brief SMPU structure (PROT_SMPU_SMPU_STRUCT13)
  */
#define CYREG_PROT_SMPU_SMPU_STRUCT13_ADDR0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR0_t*) 0x40232340UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT13_ATT0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT0_t*) 0x40232344UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT13_ADDR1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR1_t*) 0x40232360UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT13_ATT1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT1_t*) 0x40232364UL)

/**
  * \brief SMPU structure (PROT_SMPU_SMPU_STRUCT14)
  */
#define CYREG_PROT_SMPU_SMPU_STRUCT14_ADDR0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR0_t*) 0x40232380UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT14_ATT0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT0_t*) 0x40232384UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT14_ADDR1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR1_t*) 0x402323A0UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT14_ATT1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT1_t*) 0x402323A4UL)

/**
  * \brief SMPU structure (PROT_SMPU_SMPU_STRUCT15)
  */
#define CYREG_PROT_SMPU_SMPU_STRUCT15_ADDR0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR0_t*) 0x402323C0UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT15_ATT0 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT0_t*) 0x402323C4UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT15_ADDR1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ADDR1_t*) 0x402323E0UL)
#define CYREG_PROT_SMPU_SMPU_STRUCT15_ATT1 ((volatile un_PROT_SMPU_SMPU_STRUCT_ATT1_t*) 0x402323E4UL)

/**
  * \brief SMPU (PROT_SMPU0)
  */
#define CYREG_PROT_SMPU_MS0_CTL         ((volatile un_PROT_SMPU_MS0_CTL_t*) 0x40230000UL)
#define CYREG_PROT_SMPU_MS1_CTL         ((volatile un_PROT_SMPU_MS1_CTL_t*) 0x40230004UL)
#define CYREG_PROT_SMPU_MS2_CTL         ((volatile un_PROT_SMPU_MS2_CTL_t*) 0x40230008UL)
#define CYREG_PROT_SMPU_MS3_CTL         ((volatile un_PROT_SMPU_MS3_CTL_t*) 0x4023000CUL)
#define CYREG_PROT_SMPU_MS4_CTL         ((volatile un_PROT_SMPU_MS4_CTL_t*) 0x40230010UL)
#define CYREG_PROT_SMPU_MS14_CTL        ((volatile un_PROT_SMPU_MS14_CTL_t*) 0x40230038UL)
#define CYREG_PROT_SMPU_MS15_CTL        ((volatile un_PROT_SMPU_MS15_CTL_t*) 0x4023003CUL)

/**
  * \brief MPU (PROT_MPU0)
  */
#define CYREG_PROT_MPU0_MS_CTL          ((volatile un_PROT_MPU_MS_CTL_t*) 0x40234000UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR0 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234004UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR1 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234008UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR2 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023400CUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR3 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234010UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR4 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234014UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR5 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234018UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR6 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023401CUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR7 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234020UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR8 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234024UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR9 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234028UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR10 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023402CUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR11 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234030UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR12 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234034UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR13 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234038UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR14 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023403CUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR15 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234040UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR16 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234044UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR17 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234048UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR18 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023404CUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR19 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234050UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR20 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234054UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR21 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234058UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR22 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023405CUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR23 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234060UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR24 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234064UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR25 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234068UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR26 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023406CUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR27 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234070UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR28 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234074UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR29 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234078UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR30 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023407CUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR31 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234080UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR32 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234084UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR33 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234088UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR34 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023408CUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR35 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234090UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR36 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234094UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR37 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234098UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR38 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023409CUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR39 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402340A0UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR40 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402340A4UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR41 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402340A8UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR42 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402340ACUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR43 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402340B0UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR44 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402340B4UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR45 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402340B8UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR46 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402340BCUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR47 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402340C0UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR48 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402340C4UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR49 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402340C8UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR50 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402340CCUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR51 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402340D0UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR52 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402340D4UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR53 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402340D8UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR54 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402340DCUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR55 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402340E0UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR56 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402340E4UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR57 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402340E8UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR58 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402340ECUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR59 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402340F0UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR60 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402340F4UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR61 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402340F8UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR62 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402340FCUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR63 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234100UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR64 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234104UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR65 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234108UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR66 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023410CUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR67 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234110UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR68 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234114UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR69 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234118UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR70 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023411CUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR71 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234120UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR72 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234124UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR73 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234128UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR74 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023412CUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR75 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234130UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR76 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234134UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR77 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234138UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR78 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023413CUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR79 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234140UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR80 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234144UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR81 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234148UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR82 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023414CUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR83 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234150UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR84 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234154UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR85 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234158UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR86 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023415CUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR87 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234160UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR88 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234164UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR89 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234168UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR90 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023416CUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR91 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234170UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR92 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234174UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR93 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234178UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR94 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023417CUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR95 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234180UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR96 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234184UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR97 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234188UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR98 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023418CUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR99 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234190UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR100 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234194UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR101 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40234198UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR102 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023419CUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR103 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402341A0UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR104 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402341A4UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR105 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402341A8UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR106 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402341ACUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR107 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402341B0UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR108 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402341B4UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR109 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402341B8UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR110 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402341BCUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR111 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402341C0UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR112 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402341C4UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR113 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402341C8UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR114 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402341CCUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR115 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402341D0UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR116 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402341D4UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR117 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402341D8UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR118 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402341DCUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR119 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402341E0UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR120 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402341E4UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR121 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402341E8UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR122 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402341ECUL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR123 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402341F0UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR124 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402341F4UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR125 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402341F8UL)
#define CYREG_PROT_MPU0_MS_CTL_READ_MIR126 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402341FCUL)

/**
  * \brief MPU (PROT_MPU14)
  */
#define CYREG_PROT_MPU14_MS_CTL         ((volatile un_PROT_MPU_MS_CTL_t*) 0x40237800UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR0 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237804UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR1 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237808UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR2 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023780CUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR3 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237810UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR4 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237814UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR5 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237818UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR6 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023781CUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR7 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237820UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR8 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237824UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR9 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237828UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR10 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023782CUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR11 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237830UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR12 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237834UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR13 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237838UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR14 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023783CUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR15 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237840UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR16 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237844UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR17 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237848UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR18 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023784CUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR19 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237850UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR20 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237854UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR21 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237858UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR22 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023785CUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR23 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237860UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR24 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237864UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR25 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237868UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR26 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023786CUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR27 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237870UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR28 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237874UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR29 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237878UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR30 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023787CUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR31 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237880UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR32 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237884UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR33 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237888UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR34 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023788CUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR35 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237890UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR36 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237894UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR37 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237898UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR38 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023789CUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR39 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402378A0UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR40 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402378A4UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR41 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402378A8UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR42 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402378ACUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR43 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402378B0UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR44 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402378B4UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR45 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402378B8UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR46 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402378BCUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR47 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402378C0UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR48 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402378C4UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR49 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402378C8UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR50 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402378CCUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR51 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402378D0UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR52 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402378D4UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR53 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402378D8UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR54 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402378DCUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR55 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402378E0UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR56 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402378E4UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR57 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402378E8UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR58 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402378ECUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR59 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402378F0UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR60 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402378F4UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR61 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402378F8UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR62 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402378FCUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR63 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237900UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR64 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237904UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR65 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237908UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR66 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023790CUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR67 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237910UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR68 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237914UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR69 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237918UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR70 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023791CUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR71 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237920UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR72 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237924UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR73 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237928UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR74 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023792CUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR75 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237930UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR76 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237934UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR77 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237938UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR78 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023793CUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR79 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237940UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR80 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237944UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR81 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237948UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR82 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023794CUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR83 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237950UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR84 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237954UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR85 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237958UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR86 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023795CUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR87 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237960UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR88 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237964UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR89 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237968UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR90 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023796CUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR91 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237970UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR92 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237974UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR93 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237978UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR94 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023797CUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR95 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237980UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR96 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237984UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR97 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237988UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR98 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023798CUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR99 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237990UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR100 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237994UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR101 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237998UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR102 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x4023799CUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR103 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402379A0UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR104 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402379A4UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR105 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402379A8UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR106 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402379ACUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR107 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402379B0UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR108 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402379B4UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR109 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402379B8UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR110 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402379BCUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR111 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402379C0UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR112 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402379C4UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR113 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402379C8UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR114 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402379CCUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR115 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402379D0UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR116 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402379D4UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR117 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402379D8UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR118 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402379DCUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR119 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402379E0UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR120 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402379E4UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR121 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402379E8UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR122 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402379ECUL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR123 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402379F0UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR124 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402379F4UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR125 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402379F8UL)
#define CYREG_PROT_MPU14_MS_CTL_READ_MIR126 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x402379FCUL)

/**
  * \brief MPU structure (PROT_MPU_MPU_STRUCT0)
  */
#define CYREG_PROT_MPU15_MPU_STRUCT0_ADDR ((volatile un_PROT_MPU_MPU_STRUCT_ADDR_t*) 0x40237E00UL)
#define CYREG_PROT_MPU15_MPU_STRUCT0_ATT ((volatile un_PROT_MPU_MPU_STRUCT_ATT_t*) 0x40237E04UL)

/**
  * \brief MPU structure (PROT_MPU_MPU_STRUCT1)
  */
#define CYREG_PROT_MPU15_MPU_STRUCT1_ADDR ((volatile un_PROT_MPU_MPU_STRUCT_ADDR_t*) 0x40237E20UL)
#define CYREG_PROT_MPU15_MPU_STRUCT1_ATT ((volatile un_PROT_MPU_MPU_STRUCT_ATT_t*) 0x40237E24UL)

/**
  * \brief MPU structure (PROT_MPU_MPU_STRUCT2)
  */
#define CYREG_PROT_MPU15_MPU_STRUCT2_ADDR ((volatile un_PROT_MPU_MPU_STRUCT_ADDR_t*) 0x40237E40UL)
#define CYREG_PROT_MPU15_MPU_STRUCT2_ATT ((volatile un_PROT_MPU_MPU_STRUCT_ATT_t*) 0x40237E44UL)

/**
  * \brief MPU structure (PROT_MPU_MPU_STRUCT3)
  */
#define CYREG_PROT_MPU15_MPU_STRUCT3_ADDR ((volatile un_PROT_MPU_MPU_STRUCT_ADDR_t*) 0x40237E60UL)
#define CYREG_PROT_MPU15_MPU_STRUCT3_ATT ((volatile un_PROT_MPU_MPU_STRUCT_ATT_t*) 0x40237E64UL)

/**
  * \brief MPU structure (PROT_MPU_MPU_STRUCT4)
  */
#define CYREG_PROT_MPU15_MPU_STRUCT4_ADDR ((volatile un_PROT_MPU_MPU_STRUCT_ADDR_t*) 0x40237E80UL)
#define CYREG_PROT_MPU15_MPU_STRUCT4_ATT ((volatile un_PROT_MPU_MPU_STRUCT_ATT_t*) 0x40237E84UL)

/**
  * \brief MPU structure (PROT_MPU_MPU_STRUCT5)
  */
#define CYREG_PROT_MPU15_MPU_STRUCT5_ADDR ((volatile un_PROT_MPU_MPU_STRUCT_ADDR_t*) 0x40237EA0UL)
#define CYREG_PROT_MPU15_MPU_STRUCT5_ATT ((volatile un_PROT_MPU_MPU_STRUCT_ATT_t*) 0x40237EA4UL)

/**
  * \brief MPU structure (PROT_MPU_MPU_STRUCT6)
  */
#define CYREG_PROT_MPU15_MPU_STRUCT6_ADDR ((volatile un_PROT_MPU_MPU_STRUCT_ADDR_t*) 0x40237EC0UL)
#define CYREG_PROT_MPU15_MPU_STRUCT6_ATT ((volatile un_PROT_MPU_MPU_STRUCT_ATT_t*) 0x40237EC4UL)

/**
  * \brief MPU structure (PROT_MPU_MPU_STRUCT7)
  */
#define CYREG_PROT_MPU15_MPU_STRUCT7_ADDR ((volatile un_PROT_MPU_MPU_STRUCT_ADDR_t*) 0x40237EE0UL)
#define CYREG_PROT_MPU15_MPU_STRUCT7_ATT ((volatile un_PROT_MPU_MPU_STRUCT_ATT_t*) 0x40237EE4UL)

/**
  * \brief MPU (PROT_MPU15)
  */
#define CYREG_PROT_MPU15_MS_CTL         ((volatile un_PROT_MPU_MS_CTL_t*) 0x40237C00UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR0 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C04UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR1 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C08UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR2 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C0CUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR3 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C10UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR4 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C14UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR5 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C18UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR6 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C1CUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR7 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C20UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR8 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C24UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR9 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C28UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR10 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C2CUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR11 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C30UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR12 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C34UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR13 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C38UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR14 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C3CUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR15 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C40UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR16 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C44UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR17 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C48UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR18 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C4CUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR19 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C50UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR20 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C54UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR21 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C58UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR22 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C5CUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR23 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C60UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR24 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C64UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR25 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C68UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR26 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C6CUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR27 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C70UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR28 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C74UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR29 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C78UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR30 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C7CUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR31 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C80UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR32 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C84UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR33 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C88UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR34 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C8CUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR35 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C90UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR36 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C94UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR37 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C98UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR38 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237C9CUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR39 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237CA0UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR40 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237CA4UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR41 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237CA8UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR42 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237CACUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR43 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237CB0UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR44 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237CB4UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR45 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237CB8UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR46 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237CBCUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR47 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237CC0UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR48 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237CC4UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR49 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237CC8UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR50 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237CCCUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR51 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237CD0UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR52 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237CD4UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR53 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237CD8UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR54 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237CDCUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR55 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237CE0UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR56 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237CE4UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR57 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237CE8UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR58 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237CECUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR59 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237CF0UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR60 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237CF4UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR61 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237CF8UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR62 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237CFCUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR63 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D00UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR64 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D04UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR65 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D08UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR66 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D0CUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR67 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D10UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR68 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D14UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR69 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D18UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR70 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D1CUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR71 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D20UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR72 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D24UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR73 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D28UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR74 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D2CUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR75 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D30UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR76 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D34UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR77 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D38UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR78 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D3CUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR79 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D40UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR80 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D44UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR81 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D48UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR82 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D4CUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR83 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D50UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR84 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D54UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR85 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D58UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR86 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D5CUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR87 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D60UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR88 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D64UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR89 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D68UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR90 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D6CUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR91 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D70UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR92 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D74UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR93 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D78UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR94 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D7CUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR95 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D80UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR96 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D84UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR97 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D88UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR98 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D8CUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR99 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D90UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR100 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D94UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR101 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D98UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR102 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237D9CUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR103 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237DA0UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR104 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237DA4UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR105 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237DA8UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR106 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237DACUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR107 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237DB0UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR108 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237DB4UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR109 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237DB8UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR110 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237DBCUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR111 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237DC0UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR112 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237DC4UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR113 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237DC8UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR114 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237DCCUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR115 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237DD0UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR116 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237DD4UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR117 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237DD8UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR118 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237DDCUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR119 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237DE0UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR120 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237DE4UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR121 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237DE8UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR122 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237DECUL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR123 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237DF0UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR124 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237DF4UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR125 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237DF8UL)
#define CYREG_PROT_MPU15_MS_CTL_READ_MIR126 ((volatile un_PROT_MPU_MS_CTL_READ_MIR_t*) 0x40237DFCUL)

#endif /* _CYREG_PROT_H_ */


/* [] END OF FILE */
